Please use this identifier to cite or link to this item:
http://bibdigital.epn.edu.ec/handle/15000/3706
Title: | Hybrid clock and data recovery for a high speed transceiver implemented on a FPGA |
Authors: | Cárdenas López, Daniel Felipe |
Keywords: | DSP INTERFACES (COMPUTADORES) |
Issue Date: | Nov-2010 |
Abstract: | This article describes the clock and data recovery (CDR) subsystem for a 1.25 Gb/s transceiver prototype and 100 Mb/s transceiver and its implementation on FPGA. The CDR block is based on a hybrid approach for computing the optimum sampling instant, i.e. it uses digital signal processing techniques implemented on a logical core (FPGA) in order to extract the instantaneous phase error information and an external VCO for generating the exact sampling clock that drives the ADC at the receiver. |
URI: | http://bibdigital.epn.edu.ec/handle/15000/3706 |
Type: | Article |
Appears in Collections: | 2010 Memorias de las XXIII Jornadas en Ingeniería Eléctrica y Electrónica (2010 J - FIEE) |
Files in This Item:
File | Description | Size | Format | |
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2010AJIEE-39.pdf | 153,5 kB | Adobe PDF | View/Open |
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