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Campo DC | Valor | Lengua/Idioma |
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dc.contributor.author | Cárdenas López, Daniel Felipe | - |
dc.date.accessioned | 2011-04-07T22:14:30Z | - |
dc.date.available | 2011-04-07T22:14:30Z | - |
dc.date.issued | 2010-11 | - |
dc.identifier.uri | http://bibdigital.epn.edu.ec/handle/15000/3706 | - |
dc.description.abstract | This article describes the clock and data recovery (CDR) subsystem for a 1.25 Gb/s transceiver prototype and 100 Mb/s transceiver and its implementation on FPGA. The CDR block is based on a hybrid approach for computing the optimum sampling instant, i.e. it uses digital signal processing techniques implemented on a logical core (FPGA) in order to extract the instantaneous phase error information and an external VCO for generating the exact sampling clock that drives the ADC at the receiver. | es_ES |
dc.language.iso | eng | es_ES |
dc.rights | openAccess | - |
dc.rights.uri | https://creativecommons.org/licenses/by-nc-nd/4.0/ | - |
dc.subject | DSP | es_ES |
dc.subject | INTERFACES (COMPUTADORES) | es_ES |
dc.title | Hybrid clock and data recovery for a high speed transceiver implemented on a FPGA | es_ES |
dc.type | Article | es_ES |
Aparece en las colecciones: | 2010 Memorias de las XXIII Jornadas en Ingeniería Eléctrica y Electrónica (2010 J - FIEE) |
Ficheros en este ítem:
Fichero | Descripción | Tamaño | Formato | |
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2010AJIEE-39.pdf | 153,5 kB | Adobe PDF | Visualizar/Abrir |
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