Implementación en una FPGA de la técnica Selective Mapping para evaluar en hardware la reducción del PAPR de una señal OFDM

Abstract

In this project is studied the Peak Average Power Ratio (PAPR) problem in Orthogonal Frequency-Division Multiplexing (OFDM) signals which consists of the fact that occasionally the transmitted OFDM signal has a high-power peak regarding its mean power. Moreover, in this project are studied the techniques which allow to reduce the PAPR. Furthermore, a few OFDM applications are described to highlight OFDM importance. Specially, the technique known as Selective Mapping (SLM) is developed by simulations and hardware. Matlab was used to simulate the SLM technique and its implementation was carried out on a Xilinx Field Programmable Gate Array (FPGA). The OFDM system is proposed in which the SLM scheme is implemented in hardware using the HDL Coder tool. This tool is used to generate VHDL code, which allows to describe the behavior of the hardware proposed system.